1. Field of the Invention
The present invention relates to a microprocessor with a built-in instruction ROM type, and to be further detailed, relates to a microprocessor capable of re-executing a program from an arbitrary instruction address in resetting.
2. Description of Related Art
First, description is made on the conventional microprocessor taking MN1901 as an example from "User's Manual for High-Function CMOS Digital Signal Processor MN1901/MN1909" prepared by Matsushita Denko Co., Ltd. in reference to drawings.
FIG. 1 is a block diagram showing a configuration of a major part of the above-described microprocessor MN1901.
In FIG. 1, numeral 51 designates a parallel port (data register) used for input/output of parallel data.
Input/output signals to/from this parallel port 51 are as follows. Symbols P0 to P15 designate 16-bit parallel data input/output signals. These 16-bit parallel data input/output signals are inputted or outputted through a parallel data input/output terminal 57. Symbol PCS designates a port select signal showing that data transfer can be made through the parallel port 51 when it is of low logical level (GND). Symbol PR/W designates a port read/write control signal which shows data output from the parallel port 51 when it is of high logical level (V.sub.DD) and shows data input to the parallel port 51 when it is of low logical level (GND). Symbol PDS designates an input/output timing signal showing to perform data transfer when it is of low logical level (GND).
Numeral 52 designates an instruction memory (instruction ROM) storing instruction codes, wherein individual instructions constituting a program to be executed by this microprocessor are stored.
Numeral 53 designates an instruction pointer (program counter) pointing an address to the instruction memory 52. An instruction stored in an address of the instruction memory 52 pointed by this instruction pointer 53 is outputted from the instruction memory 52.
Numeral 54 designates an instruction register, which temporarily holds the instruction outputted from the instruction memory 52.
Numeral 55 designates a decoder and instruction execution unit, which decodes and executes the instruction held in the instruction register 54.
Numeral 56 designates a reset control unit. A signal RST0 inputted to this reset control unit 56 is a signal for resetting and starting this microprocessor when it is of low logical level (GND), and a signal RST is a reset start signal thereof.
Numerals 58 and 59 designate internal buses, and the parallel port 51 and the instruction pointer 53 are connected through these buses.
Next, description is made on operation of the conventional microprocessor having the configuration as described above.
FIG. 2 is a timing chart showing timing relation among the port select signal PCS(a) when data is written to the parallel port 51 from exterior, the port read/write control signal PR/W(b), the input/output timing signal PDS(c) and the parallel data input/output signals P0 to P15(d).
First, as shown in FIG. 2(a), the port select signal PCS is turned to the low logical level (GND), and thereby data transfer through the parallel port 51 is made possible. Next, as shown in FIG. 2(b), the port read/write control signal PR/W is turned to the low logical level (GND), and is set to the state capable of data input to the parallel port.
Thereafter, as shown in FIG. 2(c), the input/output timing signal PDS is turned temporarily to the low logical level (GND), and thereafter returned to the high logical level (V.sub.DD), and thereby, as shown in FIG. 2(d), the parallel data P0 to P15 are written to an input data buffer (not illustrated) in the parallel port 51.
FIG. 3 is a flowchart showing a procedure of reset processing.
In FIG. 3, when the reset signal RST0 to the reset control unit 56 is turned to the low logical level (GND) which is active over a period of one machine cycle or more (step S1), the signal RST which is an output of the reset control unit 56 is turned to the low logical level (GND) (step S2). Thereby, the instruction pointer 53 is reset and the content thereof is initialized to an address 0 (step S3). Accordingly, after reset has been cleared, instructions are read into the instruction register 54 in sequence from the instruction stored in the address 0 of the instruction memory 52, being executed sequentially.
FIG. 4 is a flowchart showing a procedure of a register indirect jump instruction by performing data input from the parallel port 51.
The register indirect jump instruction is executed in a manner that the parallel data P0 to P15, which is inputted from the parallel port 51 and held temporarily in a buffer memory (not illustrated) in the parallel port 51 (step S11), are transferred to the instruction pointer 53 (step S12).
Since the conventional microprocessor is constituted as described above, there has been a problem that in resetting it, the instruction pointer is reset always to the same value, and a program can be re-executed only from the fixed address of the instruction ROM wherein the program is stored.